Many processes and devices have been used to implement request transaction ordering applications over the past several years. The technical aspects of how an OCP (Open Core Protocol) specification, however, interacts with an AXI (Advanced Extensible Interface) bridge do not enable the design of transaction systems with request ordering policies. An OCP-to-AXI bridge interface allows an OCP master module to access an AXI slave module or an AXI interconnect fabric. The OCP specification allows OCP devices to be compliant to the OCP specification, but may not be compatible with each other. The OCP-to-AXI bridge has targeted the MIPS Technologies, Inc. MIPS32® 24Kf™ processor core usage of OCP revision 2.0 and release candidate 2.1 specifications. Any other OCP master may use this bridge if it is OCP compatible.
The main feature of the OCP-to-AXI Bridge includes unidirectional data transfer capabilities. The 64-bit OCP port generally includes a compliant slave interface while the 64-bit AXI port generally includes a compliant master interface. An OCP master such as a MIPS32 24Kf can connect seamlessly to an AXI slave with the assistance of a synchronous bridge with one clock input and one reset input. This connection can support 1:1 clocking on the OCP side and an N: 1 clock on the AXI side (i.e., AXI same or slower frequency as OCP). The OCP-to-AXI bridge supports signal processing commands such as, for example, OCP idle, write, and read commands. The OCP-to-AXI bridge also supports OCP incrementing, wrapping, streaming bursts, OCP data valid or accept commands, error responses, 1-16 data beats per burst, OCP precise bursts, OCP single request/multiple data burst modes and byte enable patterns having a power-of-two size in addition to an alignment to that size, for compatibility with MIPS32 24Kf processor simple byte enable modes.
The OCP bus follows the Open Core Protocol specification maintained by the Open Core Protocol International Partnership (OCP-IP™), which is a trade organization solely dedicated to OCP supporting products and services. The OCP standard is a non-proprietary openly licensed core-centric protocol that describes the system-level integration requirements of intellectual property (IP) cores. The AXI bus is a part of the AMBA protocol from ARM Limited. The AMBA standard includes the AXI, Advanced High-performance Bus (AHB), and Advanced Peripheral Bus (APB) bus specifications.
An RISC (Reduced Instruction Set Computer) processor family generally uses a bus architecture such as an OCP to access memories and peripheral devices. One example of such a processor family is produced by MIPS Technologies, Inc. LSI Logic CoreWare®, for example, utilizes a technology to support several different processors and peripheral devices. Usually such processors rely upon different common bus architectures to access their memory space. Reference design systems, however, have been developed that enable users to quickly utilize a processor with their designs. While building a reference design for the MIPS processor, the existing AMBA peripherals can be used with the MIPS processor when using an OCP-to-AXI bridge.
A problem was discovered during the designing of OCP-to-AXI bridge configurations in which re-ordering policies for requests used by the OCP specification of MIPS32 24Kf processor and AXI specifications were different. The OCP protocol uses one request phase that is shared by both read and write requests. Generally, support is provided by the MIPS32 24Kf processor for read and writes responses to be received in a different order than the requests sent. The AXI protocol has five independent channels, including a read address channel, a write address channel, a write data channel, a write response channel, and a read data channel. The read and write channels are independent so that read and write data can respectively reach their final destination in a different order than the original requests. The re-ordering rules between OCP and AXI protocols are different. The OCP requires the target device to resolve hazards while the AXI protocol requires the master device to resolve hazards. Moreover, the OCP-to-AXI Bridge should preferably ensure that the different ordering policies on both buses are well maintained.
Referring to FIG. 1, a block diagram of a prior art system 100 is illustrated indicative of an OCP-to-AXI bridge configuration that includes a MIPS24k 102 connected with an OCP bus 104 for signal transformation. The OCP bus 104 is further connected to an OCP fabric 106. The OCP fabric 106 is further colligated via an OCP bus 104 and an OCP slave 108. The OCP fabric 106 is linked to another OCP bus and an OCP wrapper 110 wherein an AMBA slave 112 is present.
To enable the reuse of AMBA peripherals, a solution is required to bridge the MIPS's OCP bus interface to the AMBA peripheral's bus interface. Such a solution would allow the peripherals to be reused without consuming valuable resources and time in modifying and verifying each individual peripheral in AMBA library to an OCP bus specification. This open core protocol to advanced extensible interface bridging systems has been referred to as an OCP-to-AXI bus bridge.
One solution to these problems may be the re-design of all slave peripherals, thereby using the same bus standard as the MIPS core, which is OCP-compatible and would eliminate the need for a bridge. Each individual slave peripheral would need modification following an OCP and MIPS32 24Kf processor request ordering policies. Moreover, each peripheral would need to be verified in a new test environment for the OCP protocol. The principles of design reuse are not used in existing approaches. The peripherals in the entire AMBA library would need their bus interfaces redesigned or at minimum an OCP wrapper added and the peripherals being re-verified. Thus, there is a need to re-design existing systems for enhanced functionality and efficiency.